Lecture #11: Latches, Flops, and Metastability Paul Hartke Phartke@stanford.edu Stanford EE121 February 14, 2002 Administrivia. Make sure to fill out TA evaluations!!! – Incentive: 5 Point bonus on Lab 6. Lab 6 is only worth 60 – Everything is anonymous. Lab 6 Prelab is due Midnight on Thursday.

• Sr Latch Schematic
• Sr Latch Notes Definition

By using NOR latch; By using NAND latch. Construction of SR Flip Flop By Using NOR Latch. ( S’R’ + SR’ ) Q n+1 = S + Q n R. Get more notes and other study material of Digital Design. Watch video lectures by visiting our YouTube channel LearnVidFun. Making the Reset input “high” and the Set input “low” reverses the latch circuit’s output state: Q “low” and Q-not “high.” This is known as the reset state of the circuit. If both inputs are placed into the “low” state, the circuit’s Q and Q-not outputs will remain in their last states, “remembering” their prior settings.

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The SR Latch

A good place to start is with the SR latch, and see how it can in principle be constructedusing feedback and combinational elements.

Figure 53 shows a set latch, i.e. a latch which can only be set.

When S is set to 1, this logical value is transferred to the output Q(after a non-zero propagation delay). The output is fed back to the input of theOR gate, so if S is now reset to 0, the gate remains set at 1.This latch can be set, but not reset.

Similarly, Figure 54 shows a reset latch, which can only be reset.

Figure 54:Reset latch.

Describe for yourself the operation of this circuit.

In general we need a latch which can both be set and reset.We consider two designs.

Figure 55 shows a NAND-based SR latch.

Note the double feedback. Like the latches above, this SR latch has two states:

The operation table for this NAND based latch is as follows:

S	R	Qt+	Zt+	mode
0	0	Qt	Qt	HOLD
0	1	0	0	RESET
1	0	1	1	SET
1	1	1	0	AMBIGUOUS

Here, Q_t refers to the current state value, and Q_t+ refers to the next state value.

In terms of equations,

This circuit is set dominant, since S=R=1 implies Q=1.

Note that Q=Zexcept when S=R=1.

If we disallow the input combination S=R=1, then the outputsQ and Z are called mixed rail, meaning that they are logically identicalbut are of opposite activation level.

So if we adopt the convention of disallowing S=R=1, we can draw the NAND-based SR latchas in Figure 56.

Figure 56:NAND-based SR latch, S=R=1 disallowed.

The state transition table for the NAND-based SR latch is as follows:

State transition tables are useful for state machine synthesis.The right two columns tell you the inputs required to effect thestate transition in the right column.

Figure 57 shows a NOR-based SR latch.

Figure 57:NOR-based SR latch.

The NOR-based SR latch is reset dominant, as can be seen from itsoperation table:

S	R	Qt+	Zt+	mode
0	0	Qt	Qt	HOLD
0	1	0	0	RESET
1	0	1	1	SET
1	1	0	1	AMBIGUOUS

In terms of equations,

This the outputs Q and Z are also mixed rail if we exclude the inputcombination S=R=1.

The state transition table for the NOR-based SR latch is:

S	R
0	or
1
1	0
1
0

In summary, we see that an SR latch can be implemented in two ways,using either NAND gates or NOR gates.

The basic features of the SR latch (independent of implementation) areas follows.

Operation table:

State transition table:

S	R
0
1	0
0	1
0

The standard circuit symbol for the SR latch is given in Figure 58.

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In digital electronics, a Latch is one kind of a logic circuit, and it is also known as a bistable-multivibrator. Because it has two stable states namely active high as well as active low. It works like a storage device by holding the data through a feedback lane. It stores 1-bit of data as long as the apparatus is activated. Once enable is declared then instantly latch can change the stored data. It constantly trials the inputs once enable signal is activated. The working of these circuits can be done in 2-states based on the enable signal being high or else low. When the latch circuit is the in an active high state, then both the i/ps are low. Similarly, when the latch circuit is then an active low state, then both the i/ps are high.

Different Types of Latches

The latches can be classified into different types which include SR Latch, Gated S-R Latch, D latch, Gated D Latch, JK Latch, and T Latch.

SR Latch

An SR (Set/Reset) latch is an asynchronous apparatus, and it works separately for control signals by depending on the S-state & R-inputs. The SR-latch using 2-NOR gates with a cross loop connection is exhibited below. These latches can be built with NAND gates also; however, the two inputs are exchanged as well as canceled. So it is called as SR’-latch.

Whenever a high input is given to the S-line of the latch, then the output Q goes high. In the feedback process, the output Q will stay high, when the S-input goes low once more. In this way, the latch works as a memory device.

Equally, a high input is given to the R-line of the latch, then the Q output goes low (and Q’ high), then the memory of the latch will effectively reset. When both the inputs of the latch are low, then it stays in its earlier set state or reset state. The state transition table or truth table of SR latch is shown below.

S	R	Q	Q’
0	0	Latch	Latch
0	1	0	1
1	0	1	0
1	1	0	0

When both inputs are high at once, there is trouble: it is being told toward concurrently generating a high Q & low Q. This generates a race condition in the circuit either flip flop achieves something in altering first will respond to the other & declares itself. Preferably, both Logic gates are equal and the device will be in an undefined condition for an indefinite stage.

Gated SR Latch

In some cases, it may be popular to order when the latch can & cannot latch. The simple extension of an SR latch is nothing but a gated SR latch. It gives an Enable line that should be driven high before information can be latched. Although a control line is necessary, the latch is not synchronous due to the inputs which can alter the output even in the middle of an enable pulse.

When the input of an Enable is low, the o/ps from the gates must also be less, therefore the Q & Q outputs stay latched toward the earlier information. Simply when the enable i/p is high can change the position of the latch, as shown in the tabular form. As the enable line is stated, a gated SR-latch is equal in the process toward an SR latch. Sometimes, an enable line is a CLK signal; however, it is a read/write strobe.

CLK	S	R	Q(t+1)
0	X	X	Q(t) (no change)
1	0	0	Q(t) (no change)
1	0	1	0
1	1	0	1
1	1	1	X

D Latch

The data latch is an easy expansion to the gated SR-latch that eliminates the chance of unacceptable states of input. Because the gated SR latch lets us fastener the output without employing the inputs of S or R, we can eliminate one of the i/ps by driving both the inputs with an opposite driver. We eliminate one input & automatically make it opposite of the residual input.

The D-latch outputs the input of the D when the Enable line is high, otherwise, the output is whatever the D input was whenever the Enable input was last high. This is the reason it is known as a transparent latch. When Enable is stated, then the latch is called as transparent and signals spread straightly through it since if it isn’t present.

E	D	Q	Q’
0	0	Latch	Latch
0	1	Latch	Latch
1	0	0	1
1	1	1	0

Gated D Latch

A gated D latch is designed simply by changing a gated SR-latch, and the only change in the gated SR-latch is that the input R must be modified to inverted S. Gated latch cannot be formed from SR-latch using NOR is shown below.

Whenever the CLK otherwise enable is high, the o/p latches anything is on the input of the D. Similarly when the CLK is low, then the D i/p for the final enable high is the output.

CLK	D	Q(t+1)
0	X	Q(t)
1	0	0
1	1	1

The circuit of the latch will not at all experience a Race state due to the only D input is reversed to offer to both the inputs. Therefore, there is no possibility for similar input state. Thus the circuit of D-latch can be securely used in several circuits.

JK Latch

The both JK latch, as well as RS latch, is similar. This latch comprises two inputs namely J and K which are shown in the following logic gate diagram. In this type of latch, the unclear state has been removed here. When the JK latch inputs are high, the output will be toggled. The only difference we can observe here is the output feedback toward inputs, which is not present in the RS-latch.

T Latch

The T latch can be formed whenever the JK latch inputs are shorted. The function of T Latch will be like this when the input of the latch is high, and then the output will be toggled.

Advantages of Latches

The advantages of latches include the following.

• The designing of latches is very flexible when we compare with FFs (flip-flops)
• The latches utilize less power.
• The performance of latch in the design of the high-speed circuit is quick because these are asynchronous within the design and there is no need of CLK signal.
• The shape of the latch is very small and occupies less area
• If the operation of latch based circuit is not finished in a set time, they borrow the necessary time from other to complete the operation
• Latches give aggressive clocking when contrasted with flip-flop circuits.

Disadvantages of Latches

Sr Latch Schematic

The disadvantages of latches include the following.

• There will be a chance of affecting the race condition, so these are less expected.
• When a latch is level sensitive, then there is a chance of meta-stability.
• Analyzing the circuit is difficult due to the property of level sensitive.
• The circuit can be tested by using an extra CAD program

Application of Latches

The applications of latches include the following.

• Generally, latches are used to keep the conditions of the bits to encode binary numbers
• Latches are single bit storage elements which are widely used in computing as well as data storage.
• Latches are used in the circuits like power gating & clock as a storage device.
• D latches are applicable for asynchronous systems like input or output ports.
• Data latches are used in synchronous two-phase systems for reducing the transit count.

Sr Latch Notes Definition

Thus, this is all about an overview of latches. These are the building blocks for sequential circuits. The designing of this can be done using logic gates. Its operation mainly depends on the input of an enable function. Here is a question for you, what are the two working states of latches?